Fin field-effect transistor (FinFET) devices include a transistor architecture that uses raised source-to-drain channel regions, referred to as fins. Known FinFET devices include fins with source/drain regions on lateral sides of the fins, so that current flows in a horizontal direction (e.g., parallel to a substrate) between source/drain regions at opposite ends of the fins in the horizontal direction. As horizontal devices are scaled down, there is reduced space for metal gate and source/drain contacts, which leads to degraded short-channel control and increased middle of the line (MOL) resistance.
Vertical field effect transistors (VFETs) are becoming viable device options for semiconductor devices beyond 7 nanometer (nm) node. VFET devices include fin channels with source/drain regions at ends of the fin channels on top and bottom sides of the fins. Current runs through the fin channels in a vertical direction (e.g., perpendicular to a substrate), for example, from a bottom source/drain region to a top source/drain region. Vertical transport architecture devices are designed to address the limitations of horizontal device architectures by, for example, decoupling gate length from the contact gate pitch, providing a FinFET-equivalent density at a larger contacted poly pitch (CPP), and providing lower MOL resistance.
Conventional VFET process flows result in strict constraints on thermal budget for downstream processing steps, such as top source/drain epitaxial growth and dopant activation annealing because a High-k Metal Gate (HKMG) module is formed before the downstream processing steps. High-temperature processes (e.g., >550° C.) for top source/drain formation cause threshold voltage (Vt) shift, inversion capacitance-based oxide-equivalent gate dielectric thickness (Tinv) increase, and Toxgl degradation (where Toxgl is a leakage current metric based on silicon oxide thickness) due to oxygen and metal diffusion into the channel. In addition, channel length (Lgate) is highly dependent on a metal gate recess processing, which causes large chip to chip variation in Lgate.
Accordingly, there is a need for a VFET structure and method of forming same that permits processing with less constraints on thermal budget.